The present invention relates to a multiscreen display circuit for dividing a display screen into a plurality of sub-screens so as to assign a plurality of available video signal sources to respective sub-screens so as to simultaneously display still images while updating the contents of the images in order with, current information, as one optional function of a television receiver.
In recent years, since image memories have become available at relatively low cost, television receivers including memory for one image field are increasing. In such television receivers, multiscreen display function is frequently provided as one of optional functions. This function corresponds to increasing the video signal sources and allows unitary still image display, in field feeding mode, for monitoring current programs broadcasted from ground broadcasting stations and satellite broadcasting stations so as to find preferred programs.
FIG. 7 is a conceptual illustration of a television receiver including a multiscreen display function for displaying information from a plurality of video signal sources. In the shown example, a video monitor screen is divided into nine sub-screens, in which are displayed six programs from ground broadcasting stations and two programs from satellite broadcasting stations and one program from a package-type medium input through a video terminal. On such sub-screens, respective selected video signal sources are tuned, in order from the channel No. 2 at the left upper sub-screen so as to obtain respective one field wide information for still image display.
Tsuji et al. "Multi-Functioning of Clear Vision Adapted Television Receiver", 1990 Television Association Annual Convention Pre-View 20-11, PP357.about.358, discusses a television receiver having a "channel search" function for multiscreen display by dividing the overall screen into 9/16 sub-screens and a "video search" function for overlapping right three sub-screens in FIG. 7 on normal dynamic image display. On the other hand, Sugimoto et al. "Digital Processing Technology in Television 6. Special Effect", Television Association Paper Vol. 33, No. 4 (1979), PP 301.about.310, discusses, in detail, about basic operation of a multiscreen display circuit (multi-freeze).
Discussion will be given herebelow about conventional multiscreen display circuits with reference to FIGS. 7 to 11. FIG. 10 is a block diagram of the conventional multiscreen display circuit. In FIG. 10, the reference numeral 1 denotes input terminals for video signal sources, 2 denotes a video signal source switching means for selecting one of a plurality of input terminals 1 for the video signal sources for outputting video signals therefrom, 3 denotes a horizontal thinning circuit portion connected to the output end of the video signal source switching means 2, 4 denotes a vertical thinning circuit portion connected to the output end of the horizontal thinning circuit portion 3, 5 denotes a display memory connected to the output end of the vertical thinning circuit portion 4, 6 denotes an image display device, such as CRT, connected to the output end of the image memory 5, 7 denotes a synchronization signal generating circuit portion for controlling horizontal and vertical synchronization, 8 denotes a read out control circuit portion for performing read out control according to horizontal and vertical synchronization signals from the synchronization signal generating circuit portion 7, 9 denotes a writing in control circuit portion for controlling writing of video signal in the video memory 5, 10 denotes a synchronization signal reproduction circuit portion for reproducing and supplying the horizontal and vertical synchronization signals of the video signal selected by the video signal source switching means 2 to the write in control circuit portion 9, and 11 denotes a signal switching control portion for switching of the video signal sources according to feeding of multiscreen display.
With respect to the multiscreen display circuit having the construction as set forth above, the operation will be discussed herebelow. The video signal source switching means 2 is controlled by the signal switching control portion 11 to select the input terminals 1 for the video signal sources, in order, according to the field feeding speed of the multiscreen display. Typical switching speed is approximately a one second interval. Since the amount of information to be written in the image memory 5 corresponds one field or one frame, further higher speed switching may be possible. However, in the practical view point, for reducing the amount of circuitry by commonly using the signal processing circuit among different signal sources, switching response time of the signal processing circuit (tuner, video signal processing, synchronization signal processing and so forth) has to be taken into account. It should be appreciated that the video signal source switching circuit 2 is illustrated as incorporating such signal processing circuit.
The horizontal thinning circuit portion 3 and the vertical thinning circuit portion 4 are the circuits for thinning the number of pixels in the horizontal direction and number of scanning lines in the vertical direction. In case of FIG. 7, in which the screen is divided into nine sub-screens, thinning is performed for one third in the vertical and horizontal directions. In the practical circuit construction, these circuits comprise a low pass filter for suppressing spatial folding distortion and a filter for spatially interleaving thinned pixels from the input signal. Final screen size compression is performed upon writing in the image memory 5. It should be noted that, in the following discussion, the ratio of thinning represents the thinning in the spacial sense. When the video signal source is an interlace signal of 262.5 lines/field, a display device A employs an interlace scanning of 262.5 lines/field, and a display device B employs an interlace scanning of 525 lines/field, thinning one line per four scanning lines from the video signal source with respect to the display device A and thinning one lines per two scanning lines of the video signal source with respect to the display device B has the same meaning spacially since both are thinning one fourth in the spacial ratio.
Operations of horizontal thinning circuit portion 3, vertical thinning circuit portion 4 and the image memory 5 will be discussed with reference to FIGS. 11A to 11D. FIGS. 11A to 11D are explanatory illustrations showing video signal processing in the conventional multiscreen display circuit. FIG. 11A shows the video signal output from the video signal source switching means 2, which contains an information for a true circle image at the center as displayed in the aspect ratio of horizontal 4: vertical 3. For the net input video signal, from which the fly-back component and the over-scanning component are removed, the horizontal scanning period is indicated as HI and the vertical scanning period is indicated as VI. In FIG. 11B, the image of thinning operation for one third by the horizontal thinning circuit portion 3 and the vertical thinning circuit portion 4 is illustrated at the left upper corner portion. After thinning, the information actually written in the image memory 5 is those for the pixels indicated in black at the intersections of the matrix form thinning patterns.
Writing operation for the image memory by the write in control circuit portion 9 will be discussed with reference to FIGS. 11C and 11D. FIG. 11D shows the memory space of the image memory 5. Corresponding to FIG. 7, the memory space is divided into three sections, i.e. h, 2h and 3h in the horizontal direction and into three sections, i.e. v, 2v and 3v in the vertical direction and thus divided into nine memory sections. The pixels of HW in the horizontal direction and VW in the vertical direction are written in the memory space at (0, 0) to (h, v) of the image memory 5 in the example of FIGS. 11A to 11D. At this time, other sections of the image memory 5 are maintained unchanged. Subsequently, the next video signal source is selected by the video signal source switching means 2. Through the similar process, the information is written in the memory section of (h, 0) to (2h, v). By repeating the similar process, information of the images of the nine video signal sources are written in respective memory sections. Next, discussion will be given for control of the read out control circuit 8. The region to be read out and displayed on the image display device 6, is the HR period in the horizontal direction and VR period in the vertical direction. The read out control circuit portion reads out image memory 5 irrespective of the write in control circuit portion 9. By this, the contents of the image memory 5 except for the portion to be updated, are displaced on the image display device 6 in a form of still images in overall screen.
It should be appreciated that the shown construction can be adapted for aspect ratios of either horizontal 4:vertical 3 or horizontal 16:vertical 9. FIG. 8 shows an example of division of screen of the image display device 6 in horizontal 4:vertical 3 (horizontal 12:vertical 9) in the prior art, and FIG. 9 shows another example of division of screen of the image display device 6 in horizontal 16:vertical 9 in the prior art.